TMS320C5535AZAY10

Produkt-Eigenschaften

Hersteller:
 Texas Instrumente
Produkt:
 DSPs
Verpackung / Etui:
 BGA-144
Serie:
 TMS320C5535
Produkttyp: DSP – Digital Signal Processors & Controllers

 

Kategorie:
Hersteller:
 Texas Instrumente
Produktkategorie: Digital Signal Processors & Controllers – DSP, DSC
Produkt:
 DSPs
Core:
 C55x
Number of Cores:
 1 Core
Maximum Clock Frequency:
 100 MHz
Verpackung / Etui:
 BGA-144
Program Memory Size:
 64 kB
Data RAM Size:
 320 kB
L1 Cache Instruction Memory:
 –
L1 Cache Data Memory:
 –
Betriebsspannung:
 1.3 V
Serie:
 TMS320C5535
Montageart:
 SMD/SMT
Minimale Betriebstemperatur:
 - 40 C
Maximale Betriebstemperatur:
 + 85 C
Verpackung:
 Tablett
Marke: Texas Instrumente
Data ROM Size: 128 kB
Entwicklungskit: TMDX5535EZDSP
I/O Voltage: 1.8 V to 3.3 V
Instruction Type: Fixed Point
Oberflächentyp: I2C, I2S, SPI, UART
Feuchtigkeitsempfindlich: Ja
Number of Timers/Counters: 3 x 32 bit
Produkttyp: DSP – Digital Signal Processors & Controllers
Fabrikpackung Menge: 160
Unterkategorie: Embedded Processors & Controllers
Versorgungsspannung - Max: 1.43 V
Versorgungsspannung - Min: 1.24 V
Watchdog Timers: Watchdog Timer

Processors

Texas Instruments Processors provide a comprehensive portfolio, proven software, and worldwide support, enabling industry-leading automotive and industrial solutions. TI is dedicated to advancing and optimizing today’s processors to meet tomorrow’s intelligence, performance, and cost requirements in automotive and industrial applications. Scalable hardware and software platforms with common code allow designers to seamlessly reuse and migrate across devices to protect future investment.

TMS320C553x Fixed-Point DSPs

Texas Instruments TMS320C553x Fixed-Point Digital Signal Processors (DSPs) are designed for low-power applications and based on the TMS320C55x DSPC55x DSP generation CPU processor core. The architecture achieves high performance and low power through increased parallelism and total focus on power savings. TI TMS320C553x DSPs support an internal bus structure composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle.

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